1. Field of the Invention
The present invention relates to integrated circuits, and, more specifically but not exclusively, to a bias circuit for adjusting timing or clock signals in memory circuits.
2. Description of the Related Art
Modern static random-access memory (SRAM) devices include one or more latching differential sense amplifiers that are designed to sense, amplify, and latch a differential bit-line signal from a memory cell. (See, e.g., U.S. Pat. Nos. 5,936,905; 6,738,296 B2; 7,623,400 B2; and 8,279,659 B2 and U.S. Patent Publication No. 2012/0195106 A1, the contents of all of which are hereby incorporated by reference.) The timing of the latch for each sense amplifier is determined by a self-timing pulse (also known as a Sense Amplifier Enable (SAE) signal) generated by a self-timing circuit, which typically includes a tracking word line (TWL) (also known as a dummy word line (DWL)) and a tracking bit line TBL (also known as a dummy bit line DBL) to mimic the signal-propagation delays that may occur on the signal paths to and from the memory cell. When the self-timing pulse arrives at the sense amplifier, the sense amplifier makes a decision based on the differential voltage on its differential inputs, relative to any offset voltage that the amplifier may have, and the decision is latched.
The operation of the sense amplifier, however, is highly sensitive to the timing of the self-timing pulse. If the sense amplifier is triggered too early (i.e., before a large-enough differential signal has developed at its inputs), then the sense amplifier may latch incorrect data. On the other hand, if the sense amplifier is triggered too late (i.e., after developing a larger differential signal on its inputs), then time is unnecessarily wasted, and the memory device operates slowly.
In a memory circuit, a number of different factors may impact the timing of the self-timing pulse for a sense amplifier. For example, the differential inputs of the sense amplifier are connected to a complementary pair of bit lines whose capacitances affect the speed of operation. If, for example, on a particular integrated-circuit die, there is more capacitance on the bit lines than the average expected bit-line capacitance, the signal will develop slower than usual. The sense amplifier must therefore be triggered later than usual. Conversely, for an integrated-circuit die having a lower bit-line capacitance than the average, the sense amplifier can be triggered earlier.
Variations in the size of a memory-cell transistor also impact the speed of operation for the sense amplifier. Because a memory-cell transistor is typically very narrow (e.g., a fraction of a micron), even the smallest variations in the width of the transistor may significantly impact the speed of the circuit. A particularly wide transistor will carry a higher current, which develops a signal on the bit lines faster. A narrower transistor, on the other hand, develops a slower output signal.
Another factor that affects the timing requirements of the sense amplifier is the resistivity of the word line that leads to the memory cells. The word line is frequently made of poly-silicon traces, which may exhibit significant sensitivity to process variations from one integrated-circuit die to another. If a poly-silicon word line has a high resistance, then the signal on that word line will develop more slowly. If the word line has a lower resistance, then the signal will develop more quickly.
To ensure proper operation of the sense amplifier under all process conditions, designers have conventionally been quite conservative in the amount of time by which the sense amplifier trigger signal is delayed. As a result, the access time for the memory circuit is slower than that which would otherwise be possible.